Semiconductors
A microelectronic-assembly application published August 6 builds its independent claims around a specific accelerator floorplan rather than a generic die arrangement. The engineering question it addresses is how to carry signals past a bridge layer.
Semiconductors
A published application puts the metrology inside the bonder and lets a process model write the bonding recipe from the wafer's own topography — then feeds the post-bond result back into the next one.
Semiconductors
A published application uses the surface tension of an evaporating liquid to hold a chip against a wafer long enough to release the tool, then converts the join to a covalent bond with heat and pressure.
Semiconductors
A Micron application published July 16 describes refreshing several DRAM rows at once, then rewriting each row's usage-based-disturbance data one row at a time — because the rows sit in column segments with different repair solutions and share one set of global I/O lines.
Semiconductors
A published ASML application describes a die-placement machine that parks donor dies in machined pockets, measures both the dies and their targets, then transfers the entire set in a single relative stage move. The engineering target is the alignment step that gates advanced packaging throughput.
Semiconductors
US20260206566A1 keeps the PFETs in the front-end-of-line layer and builds the NFETs above them in the back-end-of-line stack, with the two footprints overlapping. It is the only silicon record among 52 Huawei publications that day.
Semiconductors
A published application describes implanting source/drain dopants from the back side, then activating them with a sub-400 nm nanosecond laser pulse that never reaches the finished front-side stack.
Semiconductors
A newly published application describes a stacked double-liner structure that pairs a stiff inorganic film with a softer inner layer to absorb the thermomechanical mismatch between glass cores and their via metal.
Semiconductors
A large cluster of published applications is directed at gate-all-around transistors built from mismatched NMOS and PMOS stacks and wired from the backside. The disclosed structures target the two limits of nanoribbon logic: making n and p devices each want different things, and getting power to the transistor without stealing frontside routing.
Semiconductors
An issued Intel grant in the June 30 drop is directed to a glass-layer package that mounts integrated-circuit dies on both faces and embeds a silicon bridge die in a full-thickness cavity, aiming at three-dimensional heterogeneous integration with sub-25-micrometer die-to-die pitch.
Semiconductors
A cluster of newly published applications crowds the advanced-packaging and 3D-IC corner of this week's drop. They disclose how to detach a bonded carrier with light, how to bond two surfaces with no rinse in between, and how to split a logic path across stacked device tiers.
Semiconductors
Quantum Computing Inc. (QUBT) reported in an 8-K dated June 22, 2026 that it completed the all-stock acquisition of advanced-packaging house NHanced Semiconductors for $68.1 million in cash plus stock, with up to $72.0 million in earnouts. Here is what the filing states.
Semiconductors
Hybrid bonding connects two dies by directly fusing both their dielectric surfaces and their copper pads at once, replacing solder microbumps. A granted TSMC patent describes the exact sequence.
Semiconductors
A chiplet is a small functional die that is integrated with others on a shared package or interposer instead of being built as one monolithic chip. The research shows what that buys and what it complicates.
Semiconductors
High-NA EUV raises the numerical aperture of extreme-ultraviolet lithography to print finer features for sub-2nm logic. The published research shows what the larger aperture buys and what it costs.
Semiconductors
The Foreign Direct Product rule extends U.S. export jurisdiction to foreign-made items produced with U.S. technology or tools. Applied to chips, it reaches goods that never touched American soil.
Semiconductors
Companies that take CHIPS Act incentive money agree not to materially expand advanced semiconductor capacity in foreign countries of concern. The final rule sets the definitions, thresholds, and clawbacks.
Semiconductors
High-bandwidth memory stacks DRAM dies vertically to feed AI accelerators. In December 2024 the U.S. drew an export-control line on it using bandwidth density: 3 GB/s per square millimeter.
Semiconductors
A gate-all-around nanosheet transistor wraps the gate around all four sides of stacked horizontal channel sheets, replacing the three-sided FinFET. The published research explains what the architecture demands.
Semiconductors
Backside power delivery moves a chip's power-supply wiring from the front of the wafer to the back, separating power rails from signal routing. Here is what the granted patent claims describe.
Semiconductors
An arXiv preprint describes a domain-specific RISC-V processor trimmed for Tsetlin Machine inference, with the authors reporting an average 29.7x reduction in energy consumption versus a baseline RV32IM core.
Semiconductors
A preprint posted to arXiv describes ExSpike, a full-event neuromorphic architecture implemented on a Xilinx Virtex-7 FPGA that the authors report reaches up to 281.85 GOPS/W on spiking-network workloads.
Semiconductors
A cluster of published applications addresses how to electrically isolate gate-all-around transistors as nanosheet logic scales down. The disclosed structures target the shrinking space between adjacent gates and the source/drain regions stacked above them.
Semiconductors
USTR found China's semiconductor practices actionable under Section 301 and is imposing a tariff that begins at 0 percent, rising on June 23, 2027 to a rate to be announced.
