The claim language tells a different story than the roadmap slides. "Backside power delivery" and "stacked transistors" are two of the marquee leading-edge moves, and they are usually described in marketing terms — more performance, less area. The patents describe mechanisms, and reading them is how you separate announced from filed.
Start with backside power. Conventionally, both a chip's signal wires and its power-delivery network sit above the transistors, competing for the same metal layers. Backside power delivery flips the power network to the underside of the wafer. IBM's grant US12653030B2, "Double-sided integrated circuit with electrostatic guard ring" (issued June 9, 2026; International Business Machines Corporation; CPC includes H01L23/481 through-silicon vias and H01L23/5226), is a double-sided IC structure — devices wired from both faces. The "guard ring" detail matters: build on both sides and you create new electrostatic-discharge and isolation problems the single-sided design never had, and the claim addresses one of them.
The reason backside power is worth that trouble is the voltage-drop physics. Power delivered through long, thin top-side wires sags — IR drop — and that sag limits how fast and how reliably the logic switches. Move the power network to the back, on thicker, shorter paths, and you reduce the drop while handing the top metal back to signal routing. It is one of the few changes that helps both power and performance at once, which is why every leading foundry is chasing it.
Now stacked FETs. IBM's US12653023B2, "Stacked field-effect transistor device with backside cut for top source/drain access" (issued June 9, 2026), is the area play: put an n-type and p-type transistor one on top of the other instead of side by side. The hard part is wiring the buried, upper device's source and drain — and the claim's "backside cut for top source/drain access" is precisely a method for reaching them from the underside. Notice how the two ideas converge: once you are building and wiring from the backside for power, backside access for stacked devices comes along for the ride.
Map the thicket and the inventor lists overlap — the same IBM researchers (Ruilong Xie, Brent Anderson, Kisik Choi and colleagues) appear across both grants and across the related backside-cap applications in the same June 2026 flow. That clustering is the signal: this is a coordinated portfolio around double-sided, stacked construction, not two stray ideas. White space is narrowing fast where backside power and stacked FETs intersect.
Follow the capex and the roadmaps say all three leading-edge foundries want these features at 2nm and below. The claim language says the enabling structures — double-sided wiring, backside source/drain access, the isolation rings that make double-sided safe — are being locked down now. Announced is not shipping, but the IP that has to exist before shipping is already on the grant page.