Everyone obsesses over the bandwidth in a 3D stack and forgets the power. When you stack logic on memory on interposer, the headline is data: how many bytes per second flow between the layers. But every one of those layers also has to be fed power, and in a vertical stack that power has to climb — through bonds, through vias, through bridges — to reach dies that no longer sit flat on a board next to their voltage regulators.
Intel's grant US12653047B2, "Composite bridges for 3D stacked integrated circuit power delivery" (issued June 9, 2026; Intel Corporation; CPC cluster H10W70/65 and related packaging power classes), is a claim on the power half of the stack. "Composite bridges" are structures that carry power between stacked dies, and the word that matters is composite — a single material rarely satisfies the competing demands of low resistance, mechanical strength, and thermal behavior at once.
Here is why this is hard, in plain terms. Power delivery wants thick, low-resistance conductors so voltage does not sag on the way up. Data interconnect wants fine, dense connections for bandwidth. Thermal management wants paths that pull heat out. In a flat chip these compete on one surface; in a 3D stack they compete in three dimensions, through the same congested vertical space. The bridge structures in the claim are an attempt to give power its own clean path without stealing room from data or trapping heat.
The IR-drop math is the same as on a 2D chip, just nastier vertically. Push current through a thin, long vertical path and you lose voltage, and the logic at the top of the stack browns out under load exactly when it is working hardest. Composite, lower-resistance bridges are how you keep the top of the stack supplied — the vertical analog of the backside-power-delivery move happening at the transistor level.
Map this into the broader packaging thicket and a pattern emerges: the foundries and IDMs are patenting the stack from every angle at once — bonding, thermal, data interconnect, and now power delivery. Power is the least glamorous of the four and arguably the most limiting, because a stack you cannot power cleanly is a stack you cannot clock fast. The grant flow says Intel is treating it as first-class.
So the next time a 3D-packaging roadmap promises more dies stacked higher, ask how the bottom dies feed power to the top ones. Intel's 2026 composite-bridge grant is one concrete answer, and it is a reminder that in advanced packaging, power delivery is not a footnote — it is half the structure.